(VRV32C Integer Computational Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I16
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I10
sVwid_order
p12
I10
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_C.LI
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP008_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F008_S000_I000
p34
sVdescription
p35
Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic
p36
sVpurpose
p37
VUnprivileged ISA\u000aChapter 16.5
p38
sVverif_goals
p39
VInput operands:\u000a\u000aAll bits of imm[5:0] are toggled
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F008_S000_I001
p62
sg35
Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic
p63
sg37
VUnprivileged ISA\u000aChapter 16.5
p64
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
asVrfu_list_1
p71
(lp72
sg52
(lp73
sg13
(dp74
sbtp75
a(V001_C.LUI
p76
g1
(g18
g3
Ntp77
Rp78
(dp79
g22
I2
sg8
g76
sg23
VVP_IP008_P001
p80
sg25
(dp81
sg12
I1
sg15
(lp82
(V000
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V000
p87
sg23
VVP_ISA_F008_S001_I000
p88
sg35
Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic.
p89
sg37
VUnprivileged ISA\u000aChapter 16.5
p90
sg39
VInput operands:\u000a\u000aAll bits of imm[17:12] are toggled
p91
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
a(V001
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V001
p101
sg23
VVP_ISA_F008_S001_I001
p102
sg35
Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic.
p103
sg37
VUnprivileged ISA\u000aChapter 16.5
p104
sg39
VOutput result:\u000a\u000aAll bits of rd[31:12] are toggled
p105
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
asg71
(lp111
sg52
(lp112
sg13
(dp113
sbtp114
a(V002_C.ADDI
p115
g1
(g18
g3
Ntp116
Rp117
(dp118
g22
I3
sg8
g115
sg23
VVP_IP008_P002
p119
sg25
(dp120
sg12
I2
sg15
(lp121
(V000
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V000
p126
sg23
VVP_ISA_F008_S002_I000
p127
sg35
Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic.
p128
sg37
VUnprivileged ISA\u000aChapter 16.5
p129
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p130
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp131
sg15
(lp132
sg52
(lp133
sg13
(dp134
g55
I0
ssbtp135
a(V001
p136
g1
(g29
g3
Ntp137
Rp138
(dp139
g8
V001
p140
sg23
VVP_ISA_F008_S002_I001
p141
sg35
Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic.
p142
sg37
VUnprivileged ISA\u000aChapter 16.5
p143
sg39
VInput operands:\u000a\u000aAll inputs bits of rd before instruction execution are toggled\u000aAll bits of nzimm are toggled
p144
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp145
sg15
(lp146
sg52
(lp147
sg13
(dp148
g55
I0
ssbtp149
a(V002
p150
g1
(g29
g3
Ntp151
Rp152
(dp153
g8
V002
p154
sg23
VVP_ISA_F008_S002_I002
p155
sg35
Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic.
p156
sg37
VUnprivileged ISA\u000aChapter 16.5
p157
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p158
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp159
sg15
(lp160
sg52
(lp161
sg13
(dp162
g55
I0
ssbtp163
asg71
(lp164
sg52
(lp165
sg13
(dp166
sbtp167
a(V003_C.ADDI16SP
p168
g1
(g18
g3
Ntp169
Rp170
(dp171
g22
I3
sg8
g168
sg23
VVP_IP008_P003
p172
sg25
(dp173
sg12
I3
sg15
(lp174
(V000
p175
g1
(g29
g3
Ntp176
Rp177
(dp178
g8
V000
p179
sg23
VVP_ISA_F008_S003_I000
p180
sg35
Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic.
p181
sg37
VUnprivileged ISA\u000aChapter 16.5
p182
sg39
VInput operands:\u000a\u000a+ve and -ve values of nzimm are used\u000aAll bits of nzimm[9:4] are toggled\u000aAll bits of x2 before instruction execution are toggled
p183
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp184
sg15
(lp185
sg52
(lp186
sg13
(dp187
g55
I0
ssbtp188
a(V001
p189
g1
(g29
g3
Ntp190
Rp191
(dp192
g8
V001
p193
sg23
VVP_ISA_F008_S003_I001
p194
sg35
Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic.
p195
sg37
VUnprivileged ISA\u000aChapter 16.5
p196
sg39
VOutput result:\u000a\u000aAll bits of x2 are toggled
p197
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp198
sg15
(lp199
sg52
(lp200
sg13
(dp201
g55
I0
ssbtp202
asg71
(lp203
sg52
(lp204
sg13
(dp205
sbtp206
a(V004_C.ADDI4SPN
p207
g1
(g18
g3
Ntp208
Rp209
(dp210
g22
I3
sg8
g207
sg23
VVP_IP008_P004
p211
sg25
(dp212
sg12
I4
sg15
(lp213
(V000
p214
g1
(g29
g3
Ntp215
Rp216
(dp217
g8
V000
p218
sg23
VVP_ISA_F008_S004_I000
p219
sg35
Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic.
p220
sg37
VUnprivileged ISA\u000aChapter 16.5
p221
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p222
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp223
sg15
(lp224
sg52
(lp225
sg13
(dp226
g55
I0
ssbtp227
a(V001
p228
g1
(g29
g3
Ntp229
Rp230
(dp231
g8
V001
p232
sg23
VVP_ISA_F008_S004_I001
p233
sg35
Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic.
p234
sg37
VUnprivileged ISA\u000aChapter 16.5
p235
sg39
VInput operands:\u000a\u000aAll bits of nzuimm[9:2] are toggled\u000aAll bits of x2 before instruction execution are toggled
p236
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp237
sg15
(lp238
sg52
(lp239
sg13
(dp240
g55
I0
ssbtp241
a(V002
p242
g1
(g29
g3
Ntp243
Rp244
(dp245
g8
V002
p246
sg23
VVP_ISA_F008_S004_I002
p247
sg35
Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic.
p248
sg37
VUnprivileged ISA\u000aChapter 16.5
p249
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p250
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp251
sg15
(lp252
sg52
(lp253
sg13
(dp254
g55
I0
ssbtp255
asg71
(lp256
sg52
(lp257
sg13
(dp258
sbtp259
a(V005_C.SLLI
p260
g1
(g18
g3
Ntp261
Rp262
(dp263
g22
I3
sg8
g260
sg23
VVP_IP008_P005
p264
sg25
(dp265
sg12
I5
sg15
(lp266
(V000
p267
g1
(g29
g3
Ntp268
Rp269
(dp270
g8
V000
p271
sg23
VVP_ISA_F008_S005_I000
p272
sg35
Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0.
p273
sg37
VUnprivileged ISA\u000aChapter 16.5
p274
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p275
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp276
sg15
(lp277
sg52
(lp278
sg13
(dp279
g55
I0
ssbtp280
a(V001
p281
g1
(g29
g3
Ntp282
Rp283
(dp284
g8
V001
p285
sg23
VVP_ISA_F008_S005_I001
p286
sg35
Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0.
p287
sg37
VUnprivileged ISA\u000aChapter 16.5
p288
sg39
VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled
p289
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp290
sg15
(lp291
sg52
(lp292
sg13
(dp293
g55
I0
ssbtp294
a(V002
p295
g1
(g29
g3
Ntp296
Rp297
(dp298
g8
V002
p299
sg23
VVP_ISA_F008_S005_I002
p300
sg35
Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0.
p301
sg37
VUnprivileged ISA\u000aChapter 16.5
p302
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p303
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp304
sg15
(lp305
sg52
(lp306
sg13
(dp307
g55
I0
ssbtp308
asg71
(lp309
sg52
(lp310
sg13
(dp311
sbtp312
a(V006_C.SRLI
p313
g1
(g18
g3
Ntp314
Rp315
(dp316
g22
I3
sg8
g313
sg23
VVP_IP008_P006
p317
sg25
(dp318
sg12
I6
sg15
(lp319
(V000
p320
g1
(g29
g3
Ntp321
Rp322
(dp323
g8
V000
p324
sg23
VVP_ISA_F008_S006_I000
p325
sg35
Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,
p326
sg37
VUnprivileged ISA\u000aChapter 16.5
p327
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p328
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp329
sg15
(lp330
sg52
(lp331
sg13
(dp332
g55
I0
ssbtp333
a(V001
p334
g1
(g29
g3
Ntp335
Rp336
(dp337
g8
V001
p338
sg23
VVP_ISA_F008_S006_I001
p339
sg35
Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,
p340
sg37
VUnprivileged ISA\u000aChapter 16.5
p341
sg39
VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled
p342
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp343
sg15
(lp344
sg52
(lp345
sg13
(dp346
g55
I0
ssbtp347
a(V002
p348
g1
(g29
g3
Ntp349
Rp350
(dp351
g8
V002
p352
sg23
VVP_ISA_F008_S006_I002
p353
sg35
Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0,
p354
sg37
VUnprivileged ISA\u000aChapter 16.5
p355
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p356
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp357
sg15
(lp358
sg52
(lp359
sg13
(dp360
g55
I0
ssbtp361
asg71
(lp362
sg52
(lp363
sg13
(dp364
sbtp365
a(V007_C.SRAI
p366
g1
(g18
g3
Ntp367
Rp368
(dp369
g22
I3
sg8
g366
sg23
VVP_IP008_P007
p370
sg25
(dp371
sg12
I7
sg15
(lp372
(V000
p373
g1
(g29
g3
Ntp374
Rp375
(dp376
g8
V000
p377
sg23
VVP_ISA_F008_S007_I000
p378
sg35
Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0].
p379
sg37
VUnprivileged ISA\u000aChapter 16.5
p380
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p381
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp382
sg15
(lp383
sg52
(lp384
sg13
(dp385
g55
I0
ssbtp386
a(V001
p387
g1
(g29
g3
Ntp388
Rp389
(dp390
g8
V001
p391
sg23
VVP_ISA_F008_S007_I001
p392
sg35
Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0].
p393
sg37
VUnprivileged ISA\u000aChapter 16.5
p394
sg39
VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of rd` are used\u000aAll bits of rd` before instruction execution are toggled
p395
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp396
sg15
(lp397
sg52
(lp398
sg13
(dp399
g55
I0
ssbtp400
a(V002
p401
g1
(g29
g3
Ntp402
Rp403
(dp404
g8
V002
p405
sg23
VVP_ISA_F008_S007_I002
p406
sg35
Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0].
p407
sg37
VUnprivileged ISA\u000aChapter 16.5
p408
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p409
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp410
sg15
(lp411
sg52
(lp412
sg13
(dp413
g55
I0
ssbtp414
asg71
(lp415
sg52
(lp416
sg13
(dp417
sbtp418
a(V008_C.ANDI
p419
g1
(g18
g3
Ntp420
Rp421
(dp422
g22
I3
sg8
g419
sg23
VVP_IP008_P008
p423
sg25
(dp424
sg12
I8
sg15
(lp425
(V000
p426
g1
(g29
g3
Ntp427
Rp428
(dp429
g8
V000
p430
sg23
VVP_ISA_F008_S008_I000
p431
sg35
Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number
p432
sg37
VUnprivileged ISA\u000aChapter 16.5
p433
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p434
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp435
sg15
(lp436
sg52
(lp437
sg13
(dp438
g55
I0
ssbtp439
a(V001
p440
g1
(g29
g3
Ntp441
Rp442
(dp443
g8
V001
p444
sg23
VVP_ISA_F008_S008_I001
p445
sg35
Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number
p446
sg37
VUnprivileged ISA\u000aChapter 16.5
p447
sg39
VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of imm are used\u000aAll bits of rd` before instruction execution are toggled
p448
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp449
sg15
(lp450
sg52
(lp451
sg13
(dp452
g55
I0
ssbtp453
a(V002
p454
g1
(g29
g3
Ntp455
Rp456
(dp457
g8
V002
p458
sg23
VVP_ISA_F008_S008_I002
p459
sg35
Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number
p460
sg37
VUnprivileged ISA\u000aChapter 16.5
p461
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p462
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp463
sg15
(lp464
sg52
(lp465
sg13
(dp466
g55
I0
ssbtp467
asg71
(lp468
sg52
(lp469
sg13
(dp470
sbtp471
a(V009_C.MV
p472
g1
(g18
g3
Ntp473
Rp474
(dp475
g22
I3
sg8
g472
sg23
VVP_IP008_P009
p476
sg25
(dp477
sg12
I9
sg15
(lp478
(V000
p479
g1
(g29
g3
Ntp480
Rp481
(dp482
g8
V000
p483
sg23
VVP_ISA_F008_S009_I000
p484
sg35
Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0.
p485
sg37
VUnprivileged ISA\u000aChapter 16.5
p486
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs2 == rd are used
p487
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp488
sg15
(lp489
sg52
(lp490
sg13
(dp491
g55
I0
ssbtp492
a(V001
p493
g1
(g29
g3
Ntp494
Rp495
(dp496
g8
V001
p497
sg23
VVP_ISA_F008_S009_I001
p498
sg35
Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0.
p499
sg37
VUnprivileged ISA\u000aChapter 16.5
p500
sg39
VInput operands:\u000a\u000aAll bits of rs2 are toggled
p501
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp502
sg15
(lp503
sg52
(lp504
sg13
(dp505
g55
I0
ssbtp506
a(V002
p507
g1
(g29
g3
Ntp508
Rp509
(dp510
g8
V002
p511
sg23
VVP_ISA_F008_S009_I002
p512
sg35
Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0.
p513
sg37
VUnprivileged ISA\u000aChapter 16.5
p514
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled
p515
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp516
sg15
(lp517
sg52
(lp518
sg13
(dp519
g55
I0
ssbtp520
asg71
(lp521
sg52
(lp522
sg13
(dp523
sbtp524
a(V010_C.ADD
p525
g1
(g18
g3
Ntp526
Rp527
(dp528
g22
I3
sg8
g525
sg23
VVP_IP008_P010
p529
sg25
(dp530
sg12
I10
sg15
(lp531
(V000
p532
g1
(g29
g3
Ntp533
Rp534
(dp535
g8
V000
p536
sg23
VVP_ISA_F008_S010_I000
p537
sg35
Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored
p538
sg37
VUnprivileged ISA\u000aChapter 16.5
p539
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used.
p540
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp541
sg15
(lp542
sg52
(lp543
sg13
(dp544
g55
I0
ssbtp545
a(V001
p546
g1
(g29
g3
Ntp547
Rp548
(dp549
g8
V001
p550
sg23
VVP_ISA_F008_S010_I001
p551
sg35
Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored
p552
sg37
VUnprivileged ISA\u000aChapter 16.5
p553
sg39
VInput operands:\u000a\u000a+ve,-ve and zero values of rs2 are used\u000a+ve,-ve, and zero values of rdrs1 are used\u000aAll bits of rs2 are toggled\u000aAll bits of rd before instruction execution are toggled
p554
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp555
sg15
(lp556
sg52
(lp557
sg13
(dp558
g55
I0
ssbtp559
a(V002
p560
g1
(g29
g3
Ntp561
Rp562
(dp563
g8
V002
p564
sg23
VVP_ISA_F008_S010_I002
p565
sg35
Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored
p566
sg37
VUnprivileged ISA\u000aChapter 16.5
p567
sg39
VOutput result:\u000a\u000aAll bits of rd are toggled\u000a+ve,-ve and zero values of rd are used
p568
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp569
sg15
(lp570
sg52
(lp571
sg13
(dp572
g55
I0
ssbtp573
asg71
(lp574
sg52
(lp575
sg13
(dp576
sbtp577
a(V011_C.AND
p578
g1
(g18
g3
Ntp579
Rp580
(dp581
g22
I3
sg8
g578
sg23
VVP_IP008_P011
p582
sg25
(dp583
sg12
I11
sg15
(lp584
(V000
p585
g1
(g29
g3
Ntp586
Rp587
(dp588
g8
V000
p589
sg23
VVP_ISA_F008_S011_I000
p590
sg35
Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'.
p591
sg37
VUnprivileged ISA\u000aChapter 16.5
p592
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p593
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp594
sg15
(lp595
sg52
(lp596
sg13
(dp597
g55
I0
ssbtp598
a(V001
p599
g1
(g29
g3
Ntp600
Rp601
(dp602
g8
V001
p603
sg23
VVP_ISA_F008_S011_I001
p604
sg35
Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'.
p605
sg37
VUnprivileged ISA\u000aChapter 16.5
p606
sg39
VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled
p607
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp608
sg15
(lp609
sg52
(lp610
sg13
(dp611
g55
I0
ssbtp612
a(V002
p613
g1
(g29
g3
Ntp614
Rp615
(dp616
g8
V002
p617
sg23
VVP_ISA_F008_S011_I002
p618
sg35
Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'.
p619
sg37
VUnprivileged ISA\u000aChapter 16.5
p620
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p621
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp622
sg15
(lp623
sg52
(lp624
sg13
(dp625
g55
I0
ssbtp626
asg71
(lp627
sg52
(lp628
sg13
(dp629
sbtp630
a(V012_C.OR
p631
g1
(g18
g3
Ntp632
Rp633
(dp634
g22
I3
sg8
g631
sg23
VVP_IP008_P012
p635
sg25
(dp636
sg12
I12
sg15
(lp637
(V000
p638
g1
(g29
g3
Ntp639
Rp640
(dp641
g8
V000
p642
sg23
VVP_ISA_F008_S012_I000
p643
sg35
Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'.
p644
sg37
VUnprivileged ISA\u000aChapter 16.5
p645
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p646
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp647
sg15
(lp648
sg52
(lp649
sg13
(dp650
g55
I0
ssbtp651
a(V001
p652
g1
(g29
g3
Ntp653
Rp654
(dp655
g8
V001
p656
sg23
VVP_ISA_F008_S012_I001
p657
sg35
Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'.
p658
sg37
VUnprivileged ISA\u000aChapter 16.5
p659
sg39
VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled
p660
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp661
sg15
(lp662
sg52
(lp663
sg13
(dp664
g55
I0
ssbtp665
a(V002
p666
g1
(g29
g3
Ntp667
Rp668
(dp669
g8
V002
p670
sg23
VVP_ISA_F008_S012_I002
p671
sg35
Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'.
p672
sg37
VUnprivileged ISA\u000aChapter 16.5
p673
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p674
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp675
sg15
(lp676
sg52
(lp677
sg13
(dp678
g55
I0
ssbtp679
asg71
(lp680
sg52
(lp681
sg13
(dp682
sbtp683
a(V013_C.XOR
p684
g1
(g18
g3
Ntp685
Rp686
(dp687
g22
I3
sg8
g684
sg23
VVP_IP008_P013
p688
sg25
(dp689
sg12
I13
sg15
(lp690
(V000
p691
g1
(g29
g3
Ntp692
Rp693
(dp694
g8
V000
p695
sg23
VVP_ISA_F008_S013_I000
p696
sg35
Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'.
p697
sg37
VUnprivileged ISA\u000aChapter 16.5
p698
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p699
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp700
sg15
(lp701
sg52
(lp702
sg13
(dp703
g55
I0
ssbtp704
a(V001
p705
g1
(g29
g3
Ntp706
Rp707
(dp708
g8
V001
p709
sg23
VVP_ISA_F008_S013_I001
p710
sg35
Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'.
p711
sg37
VUnprivileged ISA\u000aChapter 16.5
p712
sg39
VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled
p713
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp714
sg15
(lp715
sg52
(lp716
sg13
(dp717
g55
I0
ssbtp718
a(V002
p719
g1
(g29
g3
Ntp720
Rp721
(dp722
g8
V002
p723
sg23
VVP_ISA_F008_S013_I002
p724
sg35
Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'.
p725
sg37
VUnprivileged ISA\u000aChapter 16.5
p726
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p727
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp728
sg15
(lp729
sg52
(lp730
sg13
(dp731
g55
I0
ssbtp732
asg71
(lp733
sg52
(lp734
sg13
(dp735
sbtp736
a(V014_C.SUB
p737
g1
(g18
g3
Ntp738
Rp739
(dp740
g22
I3
sg8
g737
sg23
VVP_IP008_P014
p741
sg25
(dp742
sg12
I14
sg15
(lp743
(V000
p744
g1
(g29
g3
Ntp745
Rp746
(dp747
g8
V000
p748
sg23
VVP_ISA_F008_S014_I000
p749
sg35
Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored
p750
sg37
VUnprivileged ISA\u000aChapter 16.5
p751
sg39
VRegister operands:\u000a\u000aAll possible rd` registers are used.
p752
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp753
sg15
(lp754
sg52
(lp755
sg13
(dp756
g55
I0
ssbtp757
a(V001
p758
g1
(g29
g3
Ntp759
Rp760
(dp761
g8
V001
p762
sg23
VVP_ISA_F008_S014_I001
p763
sg35
Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored
p764
sg37
VUnprivileged ISA\u000aChapter 16.5
p765
sg39
VInput operands:\u000a\u000a+ve,-ve and zero values of rs2` are used\u000a+ve, -ve, and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled
p766
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp767
sg15
(lp768
sg52
(lp769
sg13
(dp770
g55
I0
ssbtp771
a(V002
p772
g1
(g29
g3
Ntp773
Rp774
(dp775
g8
V002
p776
sg23
VVP_ISA_F008_S014_I002
p777
sg35
Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored
p778
sg37
VUnprivileged ISA\u000aChapter 16.5
p779
sg39
VOutput result:\u000a\u000aAll bits of rd` are toggled
p780
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp781
sg15
(lp782
sg52
(lp783
sg13
(dp784
g55
I0
ssbtp785
asg71
(lp786
sg52
(lp787
sg13
(dp788
sbtp789
a(V015_C.EBREAK
p790
g1
(g18
g3
Ntp791
Rp792
(dp793
g22
I1
sg8
g790
sg23
VVP_IP008_P015
p794
sg25
(dp795
sg12
I15
sg15
(lp796
(V000
p797
g1
(g29
g3
Ntp798
Rp799
(dp800
g8
V000
p801
sg23
VVP_ISA_F008_S015_I000
p802
sg35
Vc.ebreak\u000aRaiseException(Breakpoint)\u000aExpands to ebreak.
p803
sg37
VUnprivileged ISA\u000aChapter 16.5
p804
sg39
VInstruction executed
p805
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp806
sg15
(lp807
sg52
(lp808
sg13
(dp809
g55
I0
ssbtp810
asg71
(lp811
sg52
(lp812
sg13
(dp813
sbtp814
asVrfu_list_0
p815
(lp816
sg71
(lp817
sVvptool_gitrev
p818
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p819
sVio_fmt_gitrev
p820
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p821
sVconfig_gitrev
p822
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p823
sVymlcfg_gitrev
p824
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p825
sbtp826
.